The Invention relates to the field of digital integrated circuits, and in particular relates to the design of CMOS Content-Addressable Memory (CAM) arrays. CAM arrays are a form of associative memory. In particular, the invention relates to circuitry for controlling current surge related to discharge of match detect lines in CAM arrays having parallel-pulldown match detect lines.
CMOS CAM arrays are commonly used in cache systems, and other address translation systems, of high speed computing systems. They are also useful in high-speed network routers, and many other applications known in the art of computing.
CAM arrays are characterized by circuitry capable of generating a xe2x80x9cmatchxe2x80x9d output indicating whether any location of the array contains a data pattern matching a query input, and the identity of that location. CAM arrays typically are comprised of multiple rows, each row having multiple cells. Each cell of the array typically has the ability to store a unit of data, and the ability to compare that unit of data with a unit of a query input. Compare result indications of cells of each row are combined to produce a xe2x80x9cmatchxe2x80x9d signal for the row. Match signals from each row of the multiple rows together constitute the match output of the array; these signals may be encoded or used to select data from rows of additional memory.
Cells of a row typically are also connected to a common write line. The common write line allows enabling of simultaneous data writing to each cell of the row from a set of data input, or data input-output, lines.
Each cell of a CAM array is located within a column of cells of the array. Cells of a column are connected to a common unit of the query input, and are typically also connected to a common set of data input lines for writing data to cells of the array. Writing of a cell of the array typically requires that the data input lines for the cell""s column be driven to a desired data value while the write line for the cell""s row is activated. The data input lines may or may not be common with the query input lines of a cell depending upon the cell design used.
The unit of data stored in a CAM array is often binary, having two possible content states: logic one, and logic zero. Cells of these arrays produce a match compare result if the query input is equal to the data stored in the cell, and a mismatch result otherwise. CAM arrays are known that can store three or more states: logic one, logic zero, and don""t care. Cells of these xe2x80x9cternary CAMxe2x80x9d arrays produce a match compare result if the query input is either equal to the data stored in the cell, or the cell contains a don""t care state, and a mismatch result otherwise.
Ternary CAM arrays are particularly useful in address translation systems that allow variably sized allocation units. Ternary CAM arrays are also useful for storing routing tables of network routers and switches.
CAM cells may store their data in either dynamic or static storage cells as known in the art of memory circuitry. Static storage offers the advantage that refresh circuitry is not required, and the advantage that true and complement signals may be drawn from each storage cell. Ternary Static CMOS CAM cells are known, including those illustrated in U.S. Pat. No. 6,044,005, that utilize a pair of six-transistor CMOS static RAM cells as memory elements for storing a mask bit and a data bit.
It is known that combining compare results of multiple cells of a row can be done in several ways. FIG. 1 (labeled xe2x80x9cprior artxe2x80x9d) of U.S. Pat. No. 6,044,005 illustrates a parallel pulldown configuration, wherein match line ML, connected to all cells of a row, is driven low by device T4 of any cell having a mismatch compare condition. With the parallel pulldown configuration, a match for a row occurs whenever no cell of the row is driving match line ML low. FIG. 6B of U.S. Pat. No. 6,044,005 illustrates a series-string configuration, wherein transmission device T6 couples match line ripple-input ML0 to match line ripple-output ML1 when a match compare condition occurs. The match line ripple-output of each cell (except for the last cell of the row) is connected to the match line ripple-input of a following cell of the row. With this series-string configuration, a match for a row occurs when all cells couple ripple-input to ripple-output. FIG. 8 of U.S. Pat. No. 6,175,514 illustrates a full-complimentary-combiner-gate configuration, wherein compare result signals from each cell are combined by full-complimentary CMOS NAND and NOR gates to generate a row match signal.
The full-complimentary-combiner-gate configuration is fast, but can consume more room on an integrated circuit than may be desirable. The series-string configuration can be slower than desirable. The parallel pulldown configuration can produce mismatch results quickly.
The Surge Current Problem
It is known that discharge of a CMOS signal line requires that a current flow in devices attached to the line. This current is proportional to the capacitance of the signal line, to the voltage swing of the line, and inversely proportional to the time in which the discharge takes place. For example, for a signal line having capacitance C, voltage swing of V, switching in time T, the average current required for the line to discharge is C*V/T. For a hypothetical line having one picofarad of capacitance, switching two volts in one nanosecond, this per-line discharge current is about two milliamperes.
When a CAM array having a match detect circuit of the parallel pulldown type is designed, each cell of the array typically has a pulldown device capable of sinking the entire current necessary to discharge the match detect line under worst case process, voltage, and temperature conditions. CMOS device characteristics vary significantly with process, operating voltage, and temperature. If design margins are wide, a device designed to provide worst case per-line average discharge current of two milliamperes may provide a peak best-case, single-pulldown, discharge current of five to more than ten milliamperes.
The peak discharge current produced by a given line is also a function of how many parallel pulldown devices are active at any particular cycle. In a typical array, the average line will have more than one active pulldown at any one time. These lines may have substantially greater peak discharge current than the single-pulldown case.
Content addressable memory (CAM) arrays having more than five hundred lines are known. The peak current injected into the ground bus can be expected to be proportional to the number of lines times the peak current of each line. Peak ground bus currents of many amps can occur in such arrays.
High peak ground bus currents within an integrated circuit can cause undesirable side effects. For example, high peak currents may cause voltage spikes when flowing through ground metalization resistance; these spikes may cause signals to be misinterpreted by other logic on the chips.
Voltage spikes can also couple into, and disrupt, any analog circuitry on the same integrated circuit. Modern integrated circuits frequently combine such analog circuitry as phase locked loops, delay locked loops, analog-to-digital converters, digital-to-analog converters, and switched-capacitor filters with digital logic; it is particularly necessary that voltage spikes be prevented on these mixed-signal designs.
It is therefore desirable to minimize these peak ground bus currents.
Similarly, should a complementary version be built having P-type parallel pullups in place of the pulldown devices, it is desirable to minimize peak power-bus currents.
Solution to the Problem
A CMOS CAM array has been designed that uses parallel pulldown cell architecture. The array uses a ternary, static, cell however other embodiments may use binary or dynamic cells. Each row of the array has a ground-return line and a match line, the ground-return line being separate from that of other rows of the array.
The ground-return lines of each row are connected to the parallel pulldown devices of each cell of the row. The ground-return lines of each row also connect to several other devices in each cell, such as ground connections of the static memory elements of the cells, such that the ground-return line capacitance is greater than the match line capacitance.
The row ground-return lines couple to chip ground through a resistive device, which may be an N-type MOS transistor or may be a resistor. Chip ground is routed through the array and connected to the P-wells or substrate connections, the chip ground therefore has significant capacitance to the row ground-return lines.
Operation of the parallel pulldown devices causes most match lines to be pulled down to the ground-return line for the same row. The ground-return lines charge-share with the match line capacitance, quickly producing a voltage low enough to be detected as logic zero for the row. Charge from the ground-return lines then dissipates through the resistive devices into the chip ground, thereby spreading out the discharge to chip ground over time and reducing peak discharge current.
An alternative embodiment utilizes a ground-return line that is common to two rows. This permits use of a common layout technique wherein alternate rows of memory cells are mirrored such that adjacent cells may share common power and ground lines, and minimize the need for well spacings in the array.
FIG. 1 is a schematic of an equivalent circuit of an array section, illustrating the surge current problem;
FIG. 2, a schematic diagram of a ternary CAM cell suitable for use with a parallel-pulldown match line;
FIG. 3, a schematic diagram of an array of CAM cells having surge-current limiting devices according to the present invention;
FIG. 4, a simplified schematic modeling an array section, illustrating how the surge-current limiting devices control surge currents; and
FIG. 5, a schematic diagram of a binary CAM cell for use with the surge-current limiting devices, showing substrate connections.